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ADM32F036A7
ADM32F036A7QN128Q is an intelligent motor control driver chip that integrates dual ADP32F036 controllers, a complete signal acquisition chain, an intelligent power management unit, dual 6NMOS pre drivers, dual CAN/CAN-FD controllers, and dual LIN drivers. The external power NMOS can form dual brushed/brushless motor actuators on a single chip, while achieving single line control and networking.
Datasheet →Automotive Standard
l Single source power supply
-5.5~40V
- Integrated LDO (core 1.2V, IO 5V, analog 3.0V)
- Integrated POR and BOR circuits
- Integrated charge pump circuit
l Dual high-performance 32-bit fixed-point DSP cores
- Maximum clock speed of 100MHz
-16 × 16, 32 × 32 MAC operations
-16 × 16 dual MAC operations
- Harvard bus structure
- Fast interrupt response and processing
l Dual Programmable Control Law Acceleration Unit (CLA)
-32-bit Floating Point Acceleration Unit
- Acceleration Code Parallel Execution with CPU Code
l on-chip memory resources
-2 x (18K x 16 bits) SARAM
-2 x (64K x 16 bits) Flash
-2 x (8K x 16 bits) BootROM
l 128 Secure key
l ADC
-12 bit SAR, conversion rate 4MSPS
-2 x 15 channels, with 2 temperature sensor channels
- input range 0-3V, internal reference
l operational amplifier
-2 x 1 OP, can be used for bus current detection amplification
-2 x 3 PGA, can be used for phase current detection amplification
l 2 Integrated three-phase high and low side half bridge driver circuit
-2 x 6 NMOSPre Drivers
- High side VCP power supply, no need for additional bootstrap circuit
- Low side VGL power supply, stable driving voltage
- with GDF, VDS, OTP fault protection
l Voltage comparator
-2 x 3 voltage comparators
- External or built-in 8-bit DAC voltage reference,
- Output associated TZ, supporting periodic waveform protection
l Enhanced control peripherals
-2 x 3 32-bit timing/counters
-2 x 5 16 bit timing/counters
-19 PWM outputs (internal 12 control 2x6NMOS
-2 x 2 capture units (HRCAP1)
) l Interrupts
- Up to 2 x 42 interrupts set by PIE
l Serial communication peripherals
-2 x 1 channel SPI
-2 x 1 channel IIC
-2 x 1 channel CAN/CANFD
-2 x 1 LIN/SCI controller
-2 x 1 LIN transceiver, supporting sleep and remote wake-up
l IO
-17+14 universal IOs
l Clock
-2 10M on-chip oscillators
- Quartz crystal oscillator/external input mode
- PLL multiplication coefficient 1x~12x
l supports WDT
l Supports JTAG online simulation
- Analysis and breakpoint function
- Hardware based real-time debugging
l QFN128 12.3X12.3 Encapsulation
l Temperature range -40 ℃~+125 ℃
l Passed AEC-Q100 certification
l Functional Safety Level ASIL B
