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Product Overview
ADP32F08
ADP32F08 is a high-performance 32-bit fixed-point digital processor that adopts an improved Haval bus architecture and features low power consumption and high performance. It is equipped with various types of memory and rich enhanced peripherals and communication peripherals, with a wide range of application space. Its built-in high-performance ADC makes it widely applicable in various fields, such as industrial intelligent control, wireless access to the Internet of Things, variable frequency electric drive, and general signal processing.
Datasheet →industry
Product Features
- Main frequency 100MHz (cycle 10ns)
- Low power 1.5V core, 3.3V I/O power supply
● JTAG boundary scan
- Supports IEEE standard 1149.1-1990 standard test ports and boundary scan architecture
● Efficient 32-bit central processing unit (CPU)
-16 x 16 and 32 x 32 multiply accumulate (MAC) operations
tag11} -16 x 16 dual MACs
- Harvard bus architecture
- Linkage operations
- Fast interrupt response and processing
- Unified memory programming model
- Efficient code (using C/C)++ Assembly language) on-chip memory
-64K x 16 flash memory, 18K x 16 SARAM
-1K x 16 one-time programmable (OTP) ROM boot ROM (4K x 16)
- with software boot modes (SCI, SPI, CAN, I2C, and parallel I/O)
- standard mathematical tables
● clock and system control
- on-chip oscillator/external Clock input
- Supports dynamic phase-locked loop (PLL) ratio changes
- Watchdog module
● Peripheral Interrupt Extension (PIE) module
that supports interrupts from all peripherals ● 128 bit secure key/lock
- Protecting secure memory blocks
- Preventing hardware reverse engineering
● Three 32-bit CPU timers
● Enhanced control peripherals
-16 pulse width modulation outputs
-6 high-resolution PWM (HRPWM) outputs with 150ps micro boundary positioning (MEP)
-4 capture (CAP) inputs tag11} -2 Orthogonal Encoder (QEP) interfaces
● Serial port peripherals
-2 SCI (UART) modules
-4 SPI modules
-2 Enhanced Controller Area Network (eCAN) buses
-1 I2C module
● 12 bit analog-to-digital converter (ADC), 16 channels
-2 x 8-channel inputs
-2 sample and hold
- single/synchronous conversion
- conversion rate: 160ns – 6.25MSPS
- internal or external reference
● Up to 35 individually programmable multiplexed GPIO
● Low power mode
- Supports idle (IDLE), standby (STANDBY), and pause (HALT) modes
● Advanced simulation features
- Analysis and breakpoint functionality
- Real time debugging with hardware
Package options
-100 pin thin square flat (LQFP) package
- Low power 1.5V core, 3.3V I/O power supply
● JTAG boundary scan
- Supports IEEE standard 1149.1-1990 standard test ports and boundary scan architecture
● Efficient 32-bit central processing unit (CPU)
-16 x 16 and 32 x 32 multiply accumulate (MAC) operations
tag11} -16 x 16 dual MACs
- Harvard bus architecture
- Linkage operations
- Fast interrupt response and processing
- Unified memory programming model
- Efficient code (using C/C)++ Assembly language) on-chip memory
-64K x 16 flash memory, 18K x 16 SARAM
-1K x 16 one-time programmable (OTP) ROM boot ROM (4K x 16)
- with software boot modes (SCI, SPI, CAN, I2C, and parallel I/O)
- standard mathematical tables
● clock and system control
- on-chip oscillator/external Clock input
- Supports dynamic phase-locked loop (PLL) ratio changes
- Watchdog module
● Peripheral Interrupt Extension (PIE) module
that supports interrupts from all peripherals ● 128 bit secure key/lock
- Protecting secure memory blocks
- Preventing hardware reverse engineering
● Three 32-bit CPU timers
● Enhanced control peripherals
-16 pulse width modulation outputs
-6 high-resolution PWM (HRPWM) outputs with 150ps micro boundary positioning (MEP)
-4 capture (CAP) inputs tag11} -2 Orthogonal Encoder (QEP) interfaces
● Serial port peripherals
-2 SCI (UART) modules
-4 SPI modules
-2 Enhanced Controller Area Network (eCAN) buses
-1 I2C module
● 12 bit analog-to-digital converter (ADC), 16 channels
-2 x 8-channel inputs
-2 sample and hold
- single/synchronous conversion
- conversion rate: 160ns – 6.25MSPS
- internal or external reference
● Up to 35 individually programmable multiplexed GPIO
● Low power mode
- Supports idle (IDLE), standby (STANDBY), and pause (HALT) modes
● Advanced simulation features
- Analysis and breakpoint functionality
- Real time debugging with hardware
Package options
-100 pin thin square flat (LQFP) package
