● Dual core structure
- Two A2000 32-bit CPU

-200MHz

- IEEE754 Single Precision Floating Point Unit (FPU)
- Triangle Function Accelerator (TMU)
- Viterbi/Complex Mathematics Unit (VCU-II)
● Two Programmable Control Law Accelerators (CLA)
-200MHz
- IEEE 754 Single Precision Floating Point Instruction
- Execute code
independently of the main CPU
-1MB (512KW) flash memory (ECC protected)

-204KB (102KW) RAM (ECC protected or parity protected)

- Dual zone security support for third-party development
- Identification number
● Clock and system control
- Two internal zero pin 10MHz oscillators
- on-chip crystal oscillator
- Window watchdog timer module
- Lost clock detection circuit
● 1.1V core, 3.3V I/O design
● System peripherals
- Two external memory interfaces (EMIF) supporting ASRAM and SDRAM
- Two 6-channel direct memory access (DMA) controllers
- Up to 169 independent programmable, multiplexed general-purpose input/output (GPIO) pins with input filtering function
- Extended Peripheral Interrupt Controller (ePIE)
- Supports multiple low-power modes (LPM) with external wake-up function
● Communication peripherals
- USB 2.0 (MAC+PHY)
- Supports 12 pin 3.3V compatible Universal Parallel Port (uPP) interface
- Two Controller Area Networks (CAN) Module (Pin Bootable)
- Three high-speed (up to 50MHz) SPI ports (Pin Bootable)
- Two multi-channel buffered serial ports (McBSP)
- One CAN FD bus port with flexible data rate

- Four serial communication interfaces (SCI/UART) (Pin Bootable)
- Two I2C interfaces (Pin Bootable)
● Analog subsystem
- Up to four analog-to-digital converters (ADCs))
• 16 bit mode
▷ Each is 1.1MSPS (system throughput up to 4.4MSPS)
▷ Differential input
▷ Up to 12 external channels
• 12 bit mode
▷ Each is 3.5MSPS (system throughput up to 14MSPS)
▷ Single ended input
▷ Up to 24 external channels
• Each ADC has a sample and hold (S/H) circuit
• Hardware integrated post-processing of ADC conversion
▷ Saturation offset voltage calibration
▷ Setpoint calculation error
▷ High level, low level, and zero crossing comparison with interrupt function
▷ Trigger to sampling delay acquisition
- eight 12 bit analog-to-digital converters (DACs) Reference window comparator
- Three 12 bit buffered DAC outputs
● Enhanced control peripheral
-24 pulse width modulator (PWM) channels with enhanced characteristics
-16 high-resolution pulse width modulator (HRPWM) channels
▷ 8 The A and B channels of a PWM module both have high-resolution
▷ dead zone support (at standard resolution and high resolution)
-6 enhanced acquisition (eCAP) modules
-3 enhanced orthogonal encoder pulse (eQEP) modules
-8 delta sigma filter modules (SDFM) input channels, with 2 parallel filters
per channel. 5. Standard SDFM data filtering
▷ comparator filter, used for fast response in out of range situations
● Configurable Logic Block (CLB)
- enhances existing peripheral functionality
- supports Position Manager Solution
● Functional Safety Compliance
- Developed for Functional Safety Applications
- System Functionality Meets ASIL D, IEC 61508 SIL 3, IEC 60730 C Level, and UL 1998 Level 2 Standards

- Hardware Integrity Meets ASIL B and SIL 2 Requirements

● Safety Related Certification 13}