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Product Overview
AVP32F379
A high-performance multi-core 32-bit digital signal processor with a dual core structure, built-in 2 CPUs and 2 FPUs, and powerful digital signal processing and computing capabilities. It has multiple built-in parallel and serial communication interfaces, which can facilitate interaction with the outside world. The addition of CAN-FD interface enables the chip to support high-performance and high reliability communication. The built-in multiple enhanced control peripherals and analog peripherals greatly expand the application scenarios of the chip. ADC supports both single ended 12 mode and differential 16 mode, enabling high-precision sampling and precise control.
Datasheet →industry Automotive Standard
Product Features
● Dual core structure
- Two efficient 32-bit central processing units (CPUs) (A2000 cores)
- Main frequency 200MHz (period 5ns)
- IEEE754 single precision floating-point unit (FPU)
- Trigonometric function accelerator (TMU)
- Viterbi/complex mathematical unit (VCU-II)
● Two programmable control law accelerators (CLA)
-200MHz
- IEEE 754 single precision floating-point instructions
- execute code independently of the main CPU
● on-chip memory
-512KB (256KW) or 1MB (512KW) flash memory (ECC) Protection)
-172KB (86KW) or 204KB (102KW) RAM (ECC protection or parity protection)
- Dual zone security support for third-party development
- Unique identification number
● Clock and system control
- Two internal zero pin 10MHz oscillators
- on-chip crystal oscillators
} - Window watchdog timer module
- Lost clock detection circuit
● 1.1V inner core, 3.3V I/O design
● System peripherals
- Two external memory interfaces (EMIFs) supporting ASRAM and SDRAM
- Two 6-channel direct memory access (DMA) controllers
- up to 169 independent programmable, multiplexed general-purpose input/output (GPIO) pins with input filtering capabilities
- Extended Peripheral Interrupt Controller (ePIE)
- Supports multiple low-power modes (LPMs) with external wake-up capabilities
● Communication peripherals
- USB 2.0 (MAC+PHY)
} - Supports 12 pin 3.3V compatible Universal Parallel Port (uPP) interface
- Two Controller Area Network (CAN) modules (pin bootable)
- Three high-speed (up to 50MHz) SPI ports (pin bootable)
- Two multi-channel buffered serial ports (McBSP)
- One variable rate controller area network (CAN-FD) module
- Four serial communication interfaces (SCI/UART) (pin bootable)
- Two I2C interfaces (pin bootable)
● Analog subsystem
- Up to four analog-to-digital converters (ADCs)
• 16 bit mode tag12
▷ Each is 1.1MSPS (system throughput up to 4.4MSPS)
▷ Differential input
▷ Up to 12 external channels
• 12 bit mode
▷ Each is 3.5MSPS (system throughput up to 14) MSPS)
▷ Single ended input
▷ Up to 24 external channels
• Each ADC has a sample and hold (S/H) circuit
• Hardware integrated post-processing of ADC conversion
▷ Saturation offset voltage calibration
▷ Setpoint calculation error
▷ ▷ High level, low level, and zero crossing comparisons with interrupt function
▷ Trigger to sampling delay acquisition
- Eight window comparators with 12 bit analog-to-digital converter (DAC) references
- Three 12 bit buffered DAC outputs
● Enhanced control peripherals
-24 16 high-resolution pulse width modulator (HRPWM) channels with enhanced characteristics
-
▷ 8 The A and B channels of each PWM module have high-resolution
▷ dead zone support (at standard resolution and high resolution)
-6 enhanced acquisition (eCAP) modules
-3 enhanced orthogonal encoder pulse (eQEP) modules
-8 delta sigma filter modules (SDFM) input channels, with 2 parallel filters
per channel. ▷ Standard SDFM data filtering
▷ comparator filter, used for fast response in out of range situations
● Configurable Logic Block (CLB)
- enhances existing peripheral functionality
- supports Position Manager（ Location Manager Solution
● Functional Safety Compliant
- Developed for Functional Safety Applications
- Provides documentation to help make ISO 26262 system designs compliant with ASIL D, IEC 61508 SIL 3, IEC 60730 Class C, and UL 1998 Class 2 standards
- Hardware integrity up to ASIL B and SIL Level 2
● Packaging Options: 12}
- Lead free, environmentally friendly package
-337 BGA package
-176 pin LQFP package
● Temperature options:
- S: -40 ° C to 125 ° C Junction temperature
- Q: -40 ° C to 125 ° C Under natural ventilation (AEC Q100 certification for automotive applications)
- Two efficient 32-bit central processing units (CPUs) (A2000 cores)
- Main frequency 200MHz (period 5ns)
- IEEE754 single precision floating-point unit (FPU)
- Trigonometric function accelerator (TMU)
- Viterbi/complex mathematical unit (VCU-II)
● Two programmable control law accelerators (CLA)
-200MHz
- IEEE 754 single precision floating-point instructions
- execute code independently of the main CPU
● on-chip memory
-512KB (256KW) or 1MB (512KW) flash memory (ECC) Protection)
-172KB (86KW) or 204KB (102KW) RAM (ECC protection or parity protection)
- Dual zone security support for third-party development
- Unique identification number
● Clock and system control
- Two internal zero pin 10MHz oscillators
- on-chip crystal oscillators
} - Window watchdog timer module
- Lost clock detection circuit
● 1.1V inner core, 3.3V I/O design
● System peripherals
- Two external memory interfaces (EMIFs) supporting ASRAM and SDRAM
- Two 6-channel direct memory access (DMA) controllers
- up to 169 independent programmable, multiplexed general-purpose input/output (GPIO) pins with input filtering capabilities
- Extended Peripheral Interrupt Controller (ePIE)
- Supports multiple low-power modes (LPMs) with external wake-up capabilities
● Communication peripherals
- USB 2.0 (MAC+PHY)
} - Supports 12 pin 3.3V compatible Universal Parallel Port (uPP) interface
- Two Controller Area Network (CAN) modules (pin bootable)
- Three high-speed (up to 50MHz) SPI ports (pin bootable)
- Two multi-channel buffered serial ports (McBSP)
- One variable rate controller area network (CAN-FD) module
- Four serial communication interfaces (SCI/UART) (pin bootable)
- Two I2C interfaces (pin bootable)
● Analog subsystem
- Up to four analog-to-digital converters (ADCs)
• 16 bit mode tag12
▷ Each is 1.1MSPS (system throughput up to 4.4MSPS)
▷ Differential input
▷ Up to 12 external channels
• 12 bit mode
▷ Each is 3.5MSPS (system throughput up to 14) MSPS)
▷ Single ended input
▷ Up to 24 external channels
• Each ADC has a sample and hold (S/H) circuit
• Hardware integrated post-processing of ADC conversion
▷ Saturation offset voltage calibration
▷ Setpoint calculation error
▷ ▷ High level, low level, and zero crossing comparisons with interrupt function
▷ Trigger to sampling delay acquisition
- Eight window comparators with 12 bit analog-to-digital converter (DAC) references
- Three 12 bit buffered DAC outputs
● Enhanced control peripherals
-24 16 high-resolution pulse width modulator (HRPWM) channels with enhanced characteristics
-
▷ 8 The A and B channels of each PWM module have high-resolution
▷ dead zone support (at standard resolution and high resolution)
-6 enhanced acquisition (eCAP) modules
-3 enhanced orthogonal encoder pulse (eQEP) modules
-8 delta sigma filter modules (SDFM) input channels, with 2 parallel filters
per channel. ▷ Standard SDFM data filtering
▷ comparator filter, used for fast response in out of range situations
● Configurable Logic Block (CLB)
- enhances existing peripheral functionality
- supports Position Manager（ Location Manager Solution
● Functional Safety Compliant
- Developed for Functional Safety Applications
- Provides documentation to help make ISO 26262 system designs compliant with ASIL D, IEC 61508 SIL 3, IEC 60730 Class C, and UL 1998 Class 2 standards
- Hardware integrity up to ASIL B and SIL Level 2
● Packaging Options: 12}
- Lead free, environmentally friendly package
-337 BGA package
-176 pin LQFP package
● Temperature options:
- S: -40 ° C to 125 ° C Junction temperature
- Q: -40 ° C to 125 ° C Under natural ventilation (AEC Q100 certification for automotive applications)
